We tend to only use equipment that generates it's own MCLK from the master frame sync (L/R) clock so everything in the studio just receives LRCLK and then sends out another LRCLK, BCLK and DOUT. Given there are so many PLLs in the Teensy MCU I was hoping not to add an external one, but that's always a possibility. Will try the tool and see if it does what I want. (I'm doing it this way in one of my applications) Then, in absence of an ADC xtal, Teensy can provide MCLK (using either MCLK pin or and high speed clock)īut otherwise Teensy expects BCLK and L/R clock as input. Teensy in Slave mode, ADC in Master mode, BUT ADC needs MCLK There are other ADCs that do NOT require MCLK (they generate them internally in ADC from BCLK).Īll required clocks (MCLK), BCLK, L/R clock are generated by TeensyĮxternal device provides BCLK and L/R clock and Teensy adapts to master L/R clock is derived from bit-clock by taking into account the word length in bits Some ADCs require a MCLK that is 256, 512, 0r 1024 times the BCLK. (I only use ADC terminology, but believe DAC is similar) I have the feeling, we have here some semantic issues. Have fun with your project, and BTW, it wouldn't take too much effort to convert the ADAT output into SAI/MADI/AES3 or some other more modern multi-channel audio bitstream. Phase 2 would allow sampling on the slaves, upstreamed to the master.įor clock sync, I'm exploring two modes - using a separate Master Clock input to the slaves and regenerating clocks from that, or embedding occasional timecode/sync packets into the data stream and creating a soft PLL to generate clocks. The first project from this will be a monitoring system, like an Aviom, where a master Teensy broadcasts (multicasts) monitoring channels to many slaves using the WIZ5500 and off-the shelf 10/100 switches for distribution. Why I'm posting, is that I'm working on a similar problem - I'm working on a multi-channel input/output pair of interfaces to add to the library that use TCP/UDP to transport data. Have you considered using MCLK as an input and using the timers to create the subsidiary clocks? I don't think Paul's library is deeply wedded to MCLK generation from the Teensy. Sorry I can't help with the clock timing, but solving this problem will help with some other unresolved issues in the audio library/design tool - i.e.
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